DOI: 10.1145/1095408.1095420. The Price of Performance

10.1145/1095408.1095420

Crossref journal-article

Association for Computing Machinery (ACM)

Queue (320)

Abstract

In the late 1990s, our research group at DEC was one of a growing number of teams advocating the CMP (chip multiprocessor) as an alternative to highly complex single-threaded CPUs. We were designing the Piranha system,1 which was a radical point in the CMP design space in that we used very simple cores (similar to the early RISC designs of the late ’80s) to provide a higher level of thread-level parallelism. Our main goal was to achieve the best commercial workload performance for a given silicon budget. Today, in developing Google’s computing infrastructure, our focus is broader than performance alone. The merits of a particular architecture are measured by answering the following question: Are you able to afford the computational capacity you need? The high-computational demands that are inherent in most of Google’s services have led us to develop a deep understanding of the overall cost of computing, and continually to look for hardware/software designs that optimize performance per unit of cost.

Bibliography

Barroso, L. A. (2005). The Price of Performance. Queue, 3(7), 48â53.

Authors 1

Luiz André Barroso (first)

References 10 Referenced 155

10.1145/339647.339696
Transaction Processing Performance Council. Executive summary reports for TPC-C benchmark filings; http://www.tpc.org. Transaction Processing Performance Council. Executive summary reports for TPC-C benchmark filings; http://www.tpc.org.
Hoelzle U. Dean J. and Barroso L. A. 2003. Web search for a planet: the architecture of the Google cluster. IEEE Micro Magazine (April). Hoelzle U. Dean J. and Barroso L. A. 2003. Web search for a planet: the architecture of the Google cluster. IEEE Micro Magazine (April).
10.1145/291069.291067
See Reference 3. See Reference 3.
AMD competitive server benchmarks; http://www.amd.com/us-en/Processors/ProductInformation/0 30_118_8796_8800~97051 00.html. AMD competitive server benchmarks; http://www.amd.com/us-en/Processors/ProductInformation/0 30_118_8796_8800~97051 00.html.
10.1109/MM.2005.35
Intel Corporation. Intel thread checker; http://developer.intel.com/software/products/threading/tcwin. Intel Corporation. Intel thread checker; http://developer.intel.com/software/products/threading/tcwin.
Seward J. Valgrind; http://valgrind.kde.org/. Seward J. Valgrind; http://valgrind.kde.org/.
{'volume-title': 'Proceedings of OSDI', 'author': 'Dean J.', 'key': 'e_1_2_1_10_1'} / Proceedings of OSDI by Dean J.

Dates

Type	When
Created	19 years, 9 months ago (Nov. 7, 2005, 11 a.m.)
Deposited	2 months ago (June 18, 2025, 12:08 p.m.)
Indexed	2 days, 8 hours ago (Aug. 23, 2025, 1:01 a.m.)
Issued	19 years, 11 months ago (Sept. 1, 2005)
Published	19 years, 11 months ago (Sept. 1, 2005)
Published Online	19 years, 11 months ago (Sept. 1, 2005)
Published Print	19 years, 11 months ago (Sept. 1, 2005)

Funders 0

None

BibTeX

@article{Barroso_2005, title={The Price of Performance: An Economic Case for Chip Multiprocessing}, volume={3}, ISSN={1542-7749}, url={http://dx.doi.org/10.1145/1095408.1095420}, DOI={10.1145/1095408.1095420}, number={7}, journal={Queue}, publisher={Association for Computing Machinery (ACM)}, author={Barroso, Luiz André}, year={2005}, month=sep, pages={48–53} }

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