Abstract
This paper describes our research on quantum memory devices having a single transistor structure similar to that of a double-emitter resonant-tunneling hot electron transistor (RHET). Its prototype 2×2 bit cell array was fabricated and operated at room temperature. The device used in the prototype cell had no current gain, however, and required other active devices to build static random access memory (SRAM) peripheral circuits such as a decoder and senseamplifier. We also report recent advances in the memory cell made using a double-emitter RHET which has a current gain of 8 at 77 K–suitable for logic circuits peripheral to our memory cell array. The cell's small size shows promise for use in large scale memory application.
References
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(1991)
Dates
Type | When |
---|---|
Created | 22 years, 10 months ago (Oct. 1, 2002, 4:12 p.m.) |
Deposited | 2 years, 8 months ago (Dec. 7, 2022, 12:58 p.m.) |
Indexed | 6 months ago (Feb. 21, 2025, 5:34 a.m.) |
Issued | 31 years, 7 months ago (Jan. 1, 1994) |
Published | 31 years, 7 months ago (Jan. 1, 1994) |
Published Print | 31 years, 7 months ago (Jan. 1, 1994) |
@article{Mori_1994, title={A Static Random Access Memory Cell Using a Double-Emitter Resonant-Tunneling Hot Electron Transistor for Gigabit-Plus Memory Applications}, volume={33}, ISSN={1347-4065}, url={http://dx.doi.org/10.1143/jjap.33.790}, DOI={10.1143/jjap.33.790}, number={1S}, journal={Japanese Journal of Applied Physics}, publisher={IOP Publishing}, author={Mori, Toshihiko and Muto, Shunichi and Hirotaka Tamura, Hirotaka Tamura and Naoki Yokoyama, Naoki Yokoyama}, year={1994}, month=jan, pages={790} }