Abstract
Experimental fabrication of an XMOS transistor which has two insulated gates called upper-gate and lower-gate has been performed using lateral solid-phase epitaxy of a-Si film deposited by CVD of SiH4. The fabricated XMOS transistors exhibited no punch-through effect and good controllability of the upper-gate threshold voltage by the voltage applied to the lower-gate. It was found that the measured values of the slopes on the upper-gate threshold voltage control by the lower-gate voltage showed good agreement with the calculated value of the slope derived from a simple capacitance couple model.
References
7
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Dates
Type | When |
---|---|
Created | 20 years, 6 months ago (Feb. 22, 2005, 8:40 p.m.) |
Deposited | 2 years, 8 months ago (Dec. 6, 2022, 9:26 a.m.) |
Indexed | 4 months, 3 weeks ago (April 12, 2025, 1:26 a.m.) |
Issued | 35 years, 5 months ago (April 1, 1990) |
Published | 35 years, 5 months ago (April 1, 1990) |
Published Print | 35 years, 5 months ago (April 1, 1990) |
@article{Ishii_1990, title={Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films}, volume={29}, ISSN={1347-4065}, url={http://dx.doi.org/10.1143/jjap.29.l521}, DOI={10.1143/jjap.29.l521}, number={4A}, journal={Japanese Journal of Applied Physics}, publisher={IOP Publishing}, author={Ishii, Kenichi and Hayashi, Yutaka and Sekigawa, Toshihiro}, year={1990}, month=apr, pages={L521} }