DOI: 10.1126/science.aaw5581. Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

10.1126/science.aaw5581

Crossref journal-article

American Association for the Advancement of Science (AAAS)

Science (221)

Abstract

Ionic floating-gate memories Digital implementations of artificial neural networks perform many tasks, such as image recognition and language processing, but are too energy intensive for many applications. Analog circuits that use large crossbar arrays of synaptic memory elements represent a low-power alternative, but most devices cannot update the synaptic weights uniformly or scale to large array sizes. Fuller et al. developed an integrated device, ionic floating-gate memory, that has the gate terminal of a redox transistor electrically connected to a diffusive memristor. This low-power device enabled linear and symmetric weight updates in parallel over an entire crossbar array at megahertz rates over 10 9 write-read cycles. Science , this issue p. 570

Bibliography

Fuller, E. J., Keene, S. T., Melianas, A., Wang, Z., Agarwal, S., Li, Y., Tuchman, Y., James, C. D., Marinella, M. J., Yang, J. J., Salleo, A., & Talin, A. A. (2019). Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science, 364(6440), 570â574.

Authors 12

Elliot J. Fuller (first)
Scott T. Keene (additional)
Armantas Melianas (additional)
Zhongrui Wang (additional)
Sapan Agarwal (additional)
Yiyang Li (additional)
Yaakov Tuchman (additional)
Conrad D. James (additional)
Matthew J. Marinella (additional)
J. Joshua Yang (additional)
Alberto Salleo (additional)
A. Alec Talin (additional)

References 33 Referenced 639

10.1038/nature14539
10.1038/s41928-018-0059-3
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N. P. Jouppi et al . in 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA) (ACM 2017) vol. 1 pp. 1–12.
M. J. Marinella S. Agarwal A. Hsia I. Richter R. Jacobs-Gedrim J. Niroula S. J. Plimpton E. Ipek C. D. James Multiscale co-design analysis of energy latency area and accuracy of a ReRAM analog neural training accelerator. IEEE J. Emerg. Sel. Top. Circuits Syst . 8 86–101 (2018). 10.1109/JETCAS.2018.2796379 (10.1109/JETCAS.2018.2796379)
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Dates

Type	When
Created	6 years, 3 months ago (April 25, 2019, 7:06 p.m.)
Deposited	1 year, 7 months ago (Jan. 15, 2024, 6:52 p.m.)
Indexed	4 days ago (Aug. 20, 2025, 9:01 a.m.)
Issued	6 years, 3 months ago (May 10, 2019)
Published	6 years, 3 months ago (May 10, 2019)
Published Print	6 years, 3 months ago (May 10, 2019)

Funders 3

National Science Foundation 10.13039/100000001
Region: Americas
gov (National government)
Labels4
1. U.S. National Science Foundation
2. NSF
3. US NSF
4. USA NSF
Awards1
1. 1739795
Basic Energy Sciences 10.13039/100006151
Region: Americas
gov (National government)
Labels6
1. Office of Basic Energy Sciences
2. DOE Office of Basic Energy Sciences
3. US Department of Energy's Basic Energy Sciences
4. DOE Basic Energy Sciences
5. Department of Energy Basic Energy Sciences Program
6. BES
Awards1
1. DESC0001160
Sandia National Laboratories’ Laboratory Directed Research and Development Program

BibTeX

@article{Fuller_2019, title={Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing}, volume={364}, ISSN={1095-9203}, url={http://dx.doi.org/10.1126/science.aaw5581}, DOI={10.1126/science.aaw5581}, number={6440}, journal={Science}, publisher={American Association for the Advancement of Science (AAAS)}, author={Fuller, Elliot J. and Keene, Scott T. and Melianas, Armantas and Wang, Zhongrui and Agarwal, Sapan and Li, Yiyang and Tuchman, Yaakov and James, Conrad D. and Marinella, Matthew J. and Yang, J. Joshua and Salleo, Alberto and Talin, A. Alec}, year={2019}, month=may, pages={570–574} }

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