DOI: 10.1126/science.1066192. Logic Gates and Computation from Assembled Nanowire Building Blocks

Logic Gates and Computation from Assembled Nanowire Building Blocks

10.1126/science.1066192

Crossref journal-article

American Association for the Advancement of Science (AAAS)

Science (221)

Abstract

Miniaturization in electronics through improvements in established “top-down” fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past several decades. Here we report a “bottom-up” approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale field-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.

Bibliography

Huang, Y., Duan, X., Cui, Y., Lauhon, L. J., Kim, K.-H., & Lieber, C. M. (2001). Logic Gates and Computation from Assembled Nanowire Building Blocks. Science, 294(5545), 1313â1317.

Authors 6

Yu Huang (first)
Xiangfeng Duan (additional)
Yi Cui (additional)
Lincoln J. Lauhon (additional)
Kyoung-Ha Kim (additional)
Charles M. Lieber (additional)

References 28 Referenced 1,899

R. Compano L. Molenkamp D. J. Paul Technology Roadmap for Nanoelectronics European Commission IST Programme: Future and Emerging Technologies Microelectronics Advanced Research Initiative; .
C. M. Lieber Sci. Am. (September 2001) p. 58. (10.1038/scientificamerican0901-58)
10.1038/29954
R. Martel T. Schmidt H. R. Shea T. Hertel Ph. Avouris Appl. Phys. Lett. 73 2447 (1998). (10.1063/1.122477)
P. G. Collins M. S. Arnold Ph. Avouris Science 292 706 (2001). (10.1126/science.1058782)
10.1038/46241
10.1126/science.288.5465.494
V. Derycke R. Martel J. Appenzeller Ph. Avouris Nano Letters 1 453 (2001) (Web release 26 August 2001). (10.1021/nl015606f)
10.1126/science.285.5426.391
10.1126/science.289.5482.1172
Reed M. A., Chen J., Rawlett A. M., Price D. W., Tour J. M., Appl. Phys. Lett. 286, 1550 (2001). / Appl. Phys. Lett. by Reed M. A. (2001)
10.1021/jp0009305
10.1038/35051047
10.1126/science.291.5505.851
10.1063/1.1363692
10.1126/science.291.5504.630
10.1021/ja993713u
Single-crystal p-type Si-NWs were grown by using Au nanocluster catalysts SiH 4 reactant and B 2 H 6 dopant (SiH 4 :B 2 H 6 1000:1 to 6000:1) (15). Single-crystal GaN-NWs were prepared by a laser-assisted catalytic growth with iron as the catalyst (target composition: GaN:Fe = 95:5) (17) and are naturally n-type due to nitrogen vacancies or oxygen impurities (26). The SiNW surfaces consist of a ∼1-nm-thick amorphous oxide which can be removed by HF etching (14) or increased in thickness by thermal oxidation before device assembly. The GaN-NWs have only a monolayer-thick oxide over-layer (27) making them ideal for forming crossed NW junctions. Stable solutions of Si-NWs and GaN-NWs were prepared by sonication in ethanol for 5 to 10 s. Individual and multiple crossed NW junctions were prepared by using a layer-by-layer fluidic alignment strategy (16): First Si-NWs were aligned on the Si/SiO 2 surface from the ethanol solution by using a microfluidic channel and crossed GaN-NWs were deposited by using the microfluidic channel oriented perpendicular to the original SiNW flow. Au/Ti electrical contacts (50 nm Ti; 70 nm Au) to the nanowires were defined by electron-beam lithography and electron-beam evaporation.
I - V measurements made on individual p-Si and n-GaN NWs in crossed NW devices show linear I - V behavior. The p-Si NWs have two-terminal resistances of 0.5 to 10 megohms and were determined by the SiH 4 :B 2 H 6 ratio (1000:1 to 6000:1) used during growth. The n-GaN NWs have two-terminal resistances of 50 to 500 kilohms.
The turn-on voltages of crossed NW p-n junctions were increased by Joule heating the junctions in air. Because the crossing point dominates the junction resistance (13 14) a high current will locally heat the crossing point and increase the oxide layer between crossed NWs and thereby the junction resistance/turn-on voltage. The red line in the top right inset of Fig. 1A shows the large change in turn-on voltage after passing a 10-μΑ current through the junction for about 4 min; the resistance changes of the individual NWs changed less than about 10%.
The cNW-FET on/off ratio can vary from 10 3 to 10 5 depending on the p-Si NW carrier concentration. In general p-Si NWs grown with a higher dopant ratio (SiH 4 :B 2 H 6 = 1000:1) have lower resistance and smaller on/off ratios of ∼10 3 ; those synthesized with a lower dopant ratio (6000:1) have higher resistance and larger on/off ratios of ∼10 4 to 10 5 . In addition the carrier mobility typically varies from 30 to 200 cm 2 /V-s depending on doping.
S. M. Sze Semiconductor Devices Physics and Technology (Wiley New York 1985) pp. 208–210.
P. Horowitz W. Hill The Art of Electronics (Cambridge Univ. Press Cambridge 1989).
The OR and AND gates were assembled by using p-n junctions (diode logic) and do not exhibit voltage gain; however they would show gain if implemented by using cNW-FETs. For example logic OR can be implemented with the NOR gate by reversing the 5-V bias and ground connections to the p-Si NW. The AND function could also be implemented by using cNW-FETs in parallel (versus series for OR). In addition we note that both p- and n-channel transistors are possible and would enable reduced power dissipation.
Y. Huang X. Duan & C. M. Lieber unpublished results.
J. I. Pankov T. D. Moustakas Gallium Nitride ( GaN ) I (Academic Press San Diego 1998) pp. 259–265.
N. J. Watkins G. W. Wicks Yongli Gao Appl. Phys. Lett. 75 2602 (1999). (10.1063/1.125091)
We thank H. Park for helpful discussion. C.M.L. acknowledges support of this work by the Office of Naval Research and the Defense Advanced Projects Research Agency.

Dates

Type	When
Created	23 years, 1 month ago (July 27, 2002, 5:37 a.m.)
Deposited	1 year, 7 months ago (Jan. 9, 2024, 5:38 p.m.)
Indexed	3 weeks, 6 days ago (Aug. 5, 2025, 8:57 a.m.)
Issued	23 years, 9 months ago (Nov. 9, 2001)
Published	23 years, 9 months ago (Nov. 9, 2001)
Published Print	23 years, 9 months ago (Nov. 9, 2001)

Funders 0

None

BibTeX

@article{Huang_2001, title={Logic Gates and Computation from Assembled Nanowire Building Blocks}, volume={294}, ISSN={1095-9203}, url={http://dx.doi.org/10.1126/science.1066192}, DOI={10.1126/science.1066192}, number={5545}, journal={Science}, publisher={American Association for the Advancement of Science (AAAS)}, author={Huang, Yu and Duan, Xiangfeng and Cui, Yi and Lauhon, Lincoln J. and Kim, Kyoung-Ha and Lieber, Charles M.}, year={2001}, month=nov, pages={1313–1317} }

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