DOI: 10.1109/ted.2008.2010573. Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

10.1109/ted.2008.2010573

Crossref journal-article

Institute of Electrical and Electronics Engineers (IEEE)

IEEE Transactions on Electron Devices (263)

Bibliography

Wei, L., Deng, J., Chang, L.-W., Kim, K., Chuang, C.-T., & Wong, H.-S. P. (2009). Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap. IEEE Transactions on Electron Devices, 56(2), 312â320.

Authors 6

Lan Wei (first)
Jie Deng (additional)
Li-Wen Chang (additional)
Keunwoo Kim (additional)
Ching-Te Chuang (additional)
H.-S. Philip Wong (additional)

References 25 Referenced 28

{'key': 'ref10', 'year': '0', 'journal-title': 'Maxwell 3D'} / Maxwell 3D (0)
10.1109/TED.2007.902047
10.1109/16.987117
10.1149/1.2404240
{'key': 'ref14', 'year': '0', 'journal-title': 'Taurus-Device'} / Taurus-Device (0)
10.1109/IEDM.2004.1419114
{'key': 'ref16', 'author': 'shah', 'year': '2005', 'journal-title': 'Stress Modelling of Nanoscle MOSFET'} / Stress Modelling of Nanoscle MOSFET by shah (2005)
10.1109/TNANO.2003.820780
10.1143/JJAP.43.1713
10.1109/.2005.1469250
10.1016/j.sse.2007.09.025
10.1109/IEDM.2006.346881
{'key': 'ref6', 'year': '0'} (0)
10.1109/TED.2007.894596
{'key': 'ref8', 'first-page': '329', 'article-title': 'diblock copolymer directed self-assembly for cmos device fabrication', 'volume': '6150', 'author': 'chang', 'year': '2006', 'journal-title': 'Proc 31st SPIE Int Symp Microlithography Des Process Integr Microelectron Manuf IV'} / Proc 31st SPIE Int Symp Microlithography Des Process Integr Microelectron Manuf IV / diblock copolymer directed self-assembly for cmos device fabrication by chang (2006)
10.1109/IEDM.2006.346806
10.1016/S1369-7021(06)71539-5
10.1021/ja0608141
10.1109/IEDM.2007.4418914
10.1109/TNANO.2003.820774
10.1109/VLSIT.2008.4588561
10.1109/IEDM.2007.4419041
10.1109/ICSICT.2008.4734461
10.1109/DRC.2008.4800748
{'key': 'ref25', 'article-title': 'cmos gate height scaling', 'author': 'ren', 'year': '2008', 'journal-title': 'The 9th Int Conf on Solid-State and Integrated-Circuit Technology ICSICT'} / The 9th Int Conf on Solid-State and Integrated-Circuit Technology ICSICT / cmos gate height scaling by ren (2008)

Dates

Type	When
Created	16 years, 7 months ago (Jan. 16, 2009, 11:16 a.m.)
Deposited	3 years, 10 months ago (Oct. 10, 2021, 7:59 p.m.)
Indexed	1 month, 3 weeks ago (June 25, 2025, 3:31 a.m.)
Issued	16 years, 6 months ago (Feb. 1, 2009)
Published	16 years, 6 months ago (Feb. 1, 2009)
Published Print	16 years, 6 months ago (Feb. 1, 2009)

Funders 0

None

BibTeX

@article{Wei_2009, title={Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap}, volume={56}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/ted.2008.2010573}, DOI={10.1109/ted.2008.2010573}, number={2}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Wei, Lan and Deng, Jie and Chang, Li-Wen and Kim, Keunwoo and Chuang, Ching-Te and Wong, H.-S. Philip}, year={2009}, month=feb, pages={312–320} }

JSON

{
  "indexed": {
    "date-parts": [
      [
        2025,
        6,
        25
      ]
    ],
    "date-time": "2025-06-25T07:31:45Z",
    "timestamp": 1750836705274
  },
  "reference-count": 25,
  "publisher": "Institute of Electrical and Electronics Engineers (IEEE)",
  "issue": "2",
  "license": [
    {
      "start": {
        "date-parts": [
          [
            2009,
            2,
            1
          ]
        ],
        "date-time": "2009-02-01T00:00:00Z",
        "timestamp": 1233446400000
      },
      "content-version": "vor",
      "delay-in-days": 0,
      "URL": "https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html"
    }
  ],
  "content-domain": {
    "domain": [],
    "crossmark-restriction": false
  },
  "published-print": {
    "date-parts": [
      [
        2009,
        2
      ]
    ]
  },
  "DOI": "10.1109/ted.2008.2010573",
  "type": "journal-article",
  "created": {
    "date-parts": [
      [
        2009,
        1,
        16
      ]
    ],
    "date-time": "2009-01-16T16:16:03Z",
    "timestamp": 1232122563000
  },
  "page": "312-320",
  "source": "Crossref",
  "is-referenced-by-count": 28,
  "title": "Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap",
  "prefix": "10.1109",
  "volume": "56",
  "author": [
    {
      "given": "Lan",
      "family": "Wei",
      "sequence": "first",
      "affiliation": []
    },
    {
      "given": "Jie",
      "family": "Deng",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "Li-Wen",
      "family": "Chang",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "Keunwoo",
      "family": "Kim",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "Ching-Te",
      "family": "Chuang",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "H.-S. Philip",
      "family": "Wong",
      "sequence": "additional",
      "affiliation": []
    }
  ],
  "member": "263",
  "reference": [
    {
      "key": "ref10",
      "year": "0",
      "journal-title": "Maxwell 3D"
    },
    {
      "key": "ref11",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/TED.2007.902047"
    },
    {
      "key": "ref12",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/16.987117"
    },
    {
      "key": "ref13",
      "doi-asserted-by": "publisher",
      "DOI": "10.1149/1.2404240"
    },
    {
      "key": "ref14",
      "year": "0",
      "journal-title": "Taurus-Device"
    },
    {
      "key": "ref15",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/IEDM.2004.1419114"
    },
    {
      "key": "ref16",
      "author": "shah",
      "year": "2005",
      "journal-title": "Stress Modelling of Nanoscle MOSFET"
    },
    {
      "key": "ref17",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/TNANO.2003.820780"
    },
    {
      "key": "ref18",
      "doi-asserted-by": "publisher",
      "DOI": "10.1143/JJAP.43.1713"
    },
    {
      "key": "ref19",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/.2005.1469250"
    },
    {
      "key": "ref4",
      "doi-asserted-by": "publisher",
      "DOI": "10.1016/j.sse.2007.09.025"
    },
    {
      "key": "ref3",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/IEDM.2006.346881"
    },
    {
      "key": "ref6",
      "year": "0"
    },
    {
      "key": "ref5",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/TED.2007.894596"
    },
    {
      "key": "ref8",
      "first-page": "329",
      "article-title": "diblock copolymer directed self-assembly for cmos device fabrication",
      "volume": "6150",
      "author": "chang",
      "year": "2006",
      "journal-title": "Proc 31st SPIE Int Symp Microlithography Des Process Integr Microelectron Manuf IV"
    },
    {
      "key": "ref7",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/IEDM.2006.346806"
    },
    {
      "key": "ref2",
      "doi-asserted-by": "publisher",
      "DOI": "10.1016/S1369-7021(06)71539-5"
    },
    {
      "key": "ref9",
      "doi-asserted-by": "publisher",
      "DOI": "10.1021/ja0608141"
    },
    {
      "key": "ref1",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/IEDM.2007.4418914"
    },
    {
      "key": "ref20",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/TNANO.2003.820774"
    },
    {
      "key": "ref22",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/VLSIT.2008.4588561"
    },
    {
      "key": "ref21",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/IEDM.2007.4419041"
    },
    {
      "key": "ref24",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/ICSICT.2008.4734461"
    },
    {
      "key": "ref23",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/DRC.2008.4800748"
    },
    {
      "key": "ref25",
      "article-title": "cmos gate height scaling",
      "author": "ren",
      "year": "2008",
      "journal-title": "The 9th Int Conf on Solid-State and Integrated-Circuit Technology ICSICT"
    }
  ],
  "container-title": "IEEE Transactions on Electron Devices",
  "original-title": [],
  "link": [
    {
      "URL": "http://xplorestaging.ieee.org/ielx5/16/4757346/04745795.pdf?arnumber=4745795",
      "content-type": "unspecified",
      "content-version": "vor",
      "intended-application": "similarity-checking"
    }
  ],
  "deposited": {
    "date-parts": [
      [
        2021,
        10,
        10
      ]
    ],
    "date-time": "2021-10-10T23:59:38Z",
    "timestamp": 1633910378000
  },
  "score": 1,
  "resource": {
    "primary": {
      "URL": "http://ieeexplore.ieee.org/document/4745795/"
    }
  },
  "subtitle": [],
  "short-title": [],
  "issued": {
    "date-parts": [
      [
        2009,
        2
      ]
    ]
  },
  "references-count": 25,
  "journal-issue": {
    "issue": "2"
  },
  "URL": "http://dx.doi.org/10.1109/TED.2008.2010573",
  "relation": {},
  "ISSN": [
    "0018-9383"
  ],
  "subject": [],
  "container-title-short": "IEEE Trans. Electron Devices",
  "published": {
    "date-parts": [
      [
        2009,
        2
      ]
    ]
  }
}