DOI: 10.1109/ted.2007.894596. The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

10.1109/ted.2007.894596

Crossref journal-article

Institute of Electrical and Electronics Engineers (IEEE)

IEEE Transactions on Electron Devices (263)

Bibliography

Deng, J., Kim, K., Chuang, C.-T., & Wong, H.-S. P. (2007). The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology. IEEE Transactions on Electron Devices, 54(5), 1148â1155.

Authors 4

Jie Deng (first)
Keunwoo Kim (additional)
Ching-Te Chuang (additional)
H.-S. Philip Wong (additional)

References 9 Referenced 12

10.1126/science.1057553 / Science / molecular rulers for scaling down nanostructures by hatzor (2001)
{'key': 'ref3', 'first-page': '329', 'article-title': 'diblock copolymer directed self-assembly for cmos device fabrication', 'volume': '6150', 'author': 'chang', 'year': '2006', 'journal-title': 'Proc SPIE31st SPIE International Symposium on Microlithography in Design and Process Integration for Microelectronic Manufacturing IV'} / Proc SPIE31st SPIE International Symposium on Microlithography in Design and Process Integration for Microelectronic Manufacturing IV / diblock copolymer directed self-assembly for cmos device fabrication by chang (2006)
{'key': 'ref6', 'year': '0', 'journal-title': 'Taurus-Device'} / Taurus-Device (0)
{'key': 'ref5', 'year': '0', 'journal-title': 'HSPICE'} / HSPICE (0)
10.1109/IEDM.1998.746474
10.1109/IEDM.2003.1269170
{'key': 'ref2', 'first-page': '802', 'article-title': 'performance estimation and benchmarking for carbon nanotube fets and nanodiode arrays', 'author': 'wong', 'year': '2003', 'journal-title': 'Proc Int Conf SSDM'} / Proc Int Conf SSDM / performance estimation and benchmarking for carbon nanotube fets and nanodiode arrays by wong (2003)
{'key': 'ref9', 'year': '0', 'journal-title': 'Aurora'} / Aurora (0)
10.1109/IEDM.2005.1609253

Dates

Type	When
Created	18 years, 3 months ago (April 25, 2007, 10:57 a.m.)
Deposited	1 year, 6 months ago (Feb. 13, 2024, 6:21 a.m.)
Indexed	1 year, 2 months ago (June 11, 2024, 10:14 p.m.)
Issued	18 years, 3 months ago (May 1, 2007)
Published	18 years, 3 months ago (May 1, 2007)
Published Print	18 years, 3 months ago (May 1, 2007)

Funders 0

None

BibTeX

@article{Deng_2007, title={The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology}, volume={54}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/ted.2007.894596}, DOI={10.1109/ted.2007.894596}, number={5}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Deng, Jie and Kim, Keunwoo and Chuang, Ching-Te and Wong, H.-S. Philip}, year={2007}, month=may, pages={1148–1155} }

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