DOI: 10.1109/led.2013.2290117. Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric

Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric

10.1109/led.2013.2290117

Crossref journal-article

Institute of Electrical and Electronics Engineers (IEEE)

IEEE Electron Device Letters (263)

Bibliography

Cheng, C.-H., & Chin, A. (2014). Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric. IEEE Electron Device Letters, 35(1), 138â140.

Authors 2

Chun-Hu Cheng (first)
Albert Chin (additional)

References 22 Referenced 121

10.1021/nl302049k / Nano Lett / Ferroelectricity in simple binary <formula formulatype="inline"><tex Notation="TeX">${\rm ZrO}_{2}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">${\rm HfO}_{2}$</tex></formula> by muller (2012)
{'key': 'ref11', 'first-page': '247', 'article-title': 'A 45 nm logic technology with high-<formula formulatype="inline"><tex Notation="TeX">${\\rm k}+$</tex></formula> metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% pb-free packaging', 'author': 'mistry', 'year': '2007', 'journal-title': 'Proc IEEE IEDM'} / Proc IEEE IEDM / A 45 nm logic technology with high-<formula formulatype="inline"><tex Notation="TeX">${\rm k}+$</tex></formula> metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% pb-free packaging by mistry (2007)
{'key': 'ref12', 'first-page': '194', 'article-title': 'High-performance high-<formula formulatype="inline"><tex Notation="TeX">$\\kappa$</tex></formula>/metal gates for 45 nm CMOS and beyond with gate-first processing', 'author': 'chudzik', 'year': '2007', 'journal-title': 'Proc Symp VLSI Technol'} / Proc Symp VLSI Technol / High-performance high-<formula formulatype="inline"><tex Notation="TeX">$\kappa$</tex></formula>/metal gates for 45 nm CMOS and beyond with gate-first processing by chudzik (2007)
{'key': 'ref13', 'first-page': '223', 'article-title': '80 nm polysilicon gated n-FETs with ultra-thin <formula formulatype="inline"><tex Notation="TeX">${\\rm Al}_{2}{\\rm O}_{3}$</tex></formula> gate dielectric for ULSI applications', 'author': 'buchanan', 'year': '2002', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / 80 nm polysilicon gated n-FETs with ultra-thin <formula formulatype="inline"><tex Notation="TeX">${\rm Al}_{2}{\rm O}_{3}$</tex></formula> gate dielectric for ULSI applications by buchanan (2002)
{'key': 'ref14', 'first-page': '16', 'article-title': 'High quality <formula formulatype="inline"><tex Notation="TeX">${\\rm La}_{2}{\\rm O}_{3}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">${\\rm Al}_{2}{\\rm O}_{3}$</tex></formula> gate dielectrics with equivalent oxide thickness 5?10 <formula formulatype="inline"><tex Notation="TeX">${\\rm\\AA}$</tex></formula>', 'author': 'chin', 'year': '2000', 'journal-title': 'Proc Symp VLSI Technol'} / Proc Symp VLSI Technol / High quality <formula formulatype="inline"><tex Notation="TeX">${\rm La}_{2}{\rm O}_{3}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">${\rm Al}_{2}{\rm O}_{3}$</tex></formula> gate dielectrics with equivalent oxide thickness 5?10 <formula formulatype="inline"><tex Notation="TeX">${\rm\AA}$</tex></formula> by chin (2000)
10.1080/10584589908228451
10.1109/LED.2002.1015207
10.1109/IEDM.2010.5703392
10.1002/adma.201002946
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10.1109/LED.2007.900876
{'key': 'ref6', 'first-page': '305', 'article-title': 'A comprehensive approach to DRAM power management', 'author': 'hur', 'year': '2008', 'journal-title': 'Proc IEEE Int Symp HPCA'} / Proc IEEE Int Symp HPCA / A comprehensive approach to DRAM power management by hur (2008)
10.1109/LED.2009.2034113
{'key': 'ref8', 'first-page': '795', 'article-title': 'One-transistor <formula formulatype="inline"><tex Notation="TeX">${\\rm PZT}/{\\rm Al}_{2}{\\rm O}_{3}$</tex></formula>, <formula formulatype="inline"><tex Notation="TeX">${\\rm SBT}/{\\rm Al}_{2}{\\rm O}_{3}$</tex> </formula>, and <formula formulatype="inline"><tex Notation="TeX">${\\rm BLT}/{\\rm Al}_{2}{\\rm O}_{3}$</tex></formula> stacked gate memory', 'author': 'yang', 'year': '2001', 'journal-title': 'Proc IEDM'} / Proc IEDM / One-transistor <formula formulatype="inline"><tex Notation="TeX">${\rm PZT}/{\rm Al}_{2}{\rm O}_{3}$</tex></formula>, <formula formulatype="inline"><tex Notation="TeX">${\rm SBT}/{\rm Al}_{2}{\rm O}_{3}$</tex> </formula>, and <formula formulatype="inline"><tex Notation="TeX">${\rm BLT}/{\rm Al}_{2}{\rm O}_{3}$</tex></formula> stacked gate memory by yang (2001)
10.1557/mrs2004.235
10.1109/TED.2006.881013
{'key': 'ref1', 'year': '2011', 'journal-title': 'International Technology Roadmap for Semiconductors (ITRS)'} / International Technology Roadmap for Semiconductors (ITRS) (2011)
10.1038/nmat3649
{'key': 'ref20', 'first-page': '181', 'article-title': '3D GOI CMOSFETs with novel <formula formulatype="inline"><tex Notation="TeX">${\\rm IrO}_{2}$</tex></formula> (Hf) dual gates and high-<formula formulatype="inline"><tex Notation="TeX">$\\kappa$</tex></formula> dielectric on 1P6M-0.18 <formula formulatype="inline"> <tex Notation="TeX">$\\mu{\\rm m}$</tex></formula>-CMOS', 'author': 'yu', 'year': '2004', 'journal-title': 'Proc IEEE IEDM'} / Proc IEEE IEDM / 3D GOI CMOSFETs with novel <formula formulatype="inline"><tex Notation="TeX">${\rm IrO}_{2}$</tex></formula> (Hf) dual gates and high-<formula formulatype="inline"><tex Notation="TeX">$\kappa$</tex></formula> dielectric on 1P6M-0.18 <formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula>-CMOS by yu (2004)
10.1109/LED.2011.2177435
{'key': 'ref21', 'first-page': '161', 'article-title': 'A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85<formula formulatype="inline"> <tex Notation="TeX">$^{\\circ}{\\rm C}$</tex></formula>', 'author': 'collaert', 'year': '2010', 'journal-title': 'Proc Symp VLSI Technol'} / Proc Symp VLSI Technol / A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85<formula formulatype="inline"> <tex Notation="TeX">$^{\circ}{\rm C}$</tex></formula> by collaert (2010)

Dates

Type	When
Created	11 years, 7 months ago (Jan. 3, 2014, 2:21 p.m.)
Deposited	3 years, 7 months ago (Jan. 12, 2022, 11:24 a.m.)
Indexed	2 months ago (June 19, 2025, 12:27 p.m.)
Issued	11 years, 7 months ago (Jan. 1, 2014)
Published	11 years, 7 months ago (Jan. 1, 2014)
Published Print	11 years, 7 months ago (Jan. 1, 2014)

Funders 0

None

BibTeX

@article{Cheng_2014, title={Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric}, volume={35}, ISSN={1558-0563}, url={http://dx.doi.org/10.1109/led.2013.2290117}, DOI={10.1109/led.2013.2290117}, number={1}, journal={IEEE Electron Device Letters}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Cheng, Chun-Hu and Chin, Albert}, year={2014}, month=jan, pages={138–140} }

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