DOI: 10.1109/cicc.2000.852648. New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

10.1109/cicc.2000.852648

Crossref proceedings-article

IEEE

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) (263)

Bibliography

Cao, Y., Sato, T., Orshansky, M., Sylvester, D., & Hu, C. (n.d.). New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 201â204.

Authors 5

Y. Cao (first)
T. Sato (additional)
M. Orshansky (additional)
D. Sylvester (additional)
C. Hu (additional)

References 12 Referenced 237

{'journal-title': 'Prediction of Next Generation Device Models for Technology Development and Early Circuit Design', 'year': '0', 'author': 'orshansky', 'key': 'ref4'} / Prediction of Next Generation Device Models for Technology Development and Early Circuit Design by orshansky (0)
{'key': 'ref3', 'article-title': 'Pre-Silicon Parameter Generation Methodology using BSIM3v3 for Device/Circuit Concurrent Design', 'author': 'miyama', 'year': '0', 'journal-title': 'Proceedings of the IEEE 1999 CICC'} / Proceedings of the IEEE 1999 CICC / Pre-Silicon Parameter Generation Methodology using BSIM3v3 for Device/Circuit Concurrent Design by miyama (0)
{'key': 'ref10', 'first-page': '148', 'article-title': 'Optimization of a 0.18?m 1.5V CMOS Technology to Achieve 15ps Gate Delay', 'author': 'yang', 'year': '1998', 'journal-title': 'Symposium on VLSI Technology'} / Symposium on VLSI Technology / Optimization of a 0.18?m 1.5V CMOS Technology to Achieve 15ps Gate Delay by yang (1998)
{'key': 'ref6', 'first-page': '18', 'article-title': 'A High-Performance Sub-0.25?m CMOS Technology with Multiple Thresholds and Copper Interconnects', 'author': 'su', 'year': '1998', 'journal-title': 'Symposium on VLSI Technology'} / Symposium on VLSI Technology / A High-Performance Sub-0.25?m CMOS Technology with Multiple Thresholds and Copper Interconnects by su (1998)
{'key': 'ref11', 'first-page': '51', 'article-title': 'A Source/Drain Formation Technology Utilizing Sub-10keV Arsenic and Assiat-Phosphorus Implantation for 0.13?m MOSFET', 'author': 'imai', 'year': '1999', 'journal-title': 'Symposium on VLSI Technology'} / Symposium on VLSI Technology / A Source/Drain Formation Technology Utilizing Sub-10keV Arsenic and Assiat-Phosphorus Implantation for 0.13?m MOSFET by imai (1999)
10.1109/IEDM.1996.554112
10.1109/IEDM.1996.554112
10.1109/IEDM.1996.554046
10.1109/IEDM.1997.650509
{'journal-title': 'BSIM3v3 Manual', 'year': '1996', 'key': 'ref2'} / BSIM3v3 Manual (1996)
10.1109/IEDM.1998.746320
{'year': '0', 'key': 'ref1'} (0)

Dates

Type	When
Created	22 years, 9 months ago (Nov. 7, 2002, 4:22 p.m.)
Deposited	8 years, 5 months ago (March 10, 2017, 7:03 p.m.)
Indexed	3 days, 6 hours ago (Aug. 28, 2025, 8:51 a.m.)

Funders 0

None

BibTeX

@inproceedings{Cao, series={CICC-00}, title={New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation}, url={http://dx.doi.org/10.1109/cicc.2000.852648}, DOI={10.1109/cicc.2000.852648}, booktitle={Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)}, publisher={IEEE}, author={Cao, Y. and Sato, T. and Orshansky, M. and Sylvester, D. and Hu, C.}, pages={201–204}, collection={CICC-00} }

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