DOI: 10.1109/5.915374. Device scaling limits of Si MOSFETs and their application dependencies

Device scaling limits of Si MOSFETs and their application dependencies

10.1109/5.915374

Crossref journal-article

Institute of Electrical and Electronics Engineers (IEEE)

Proceedings of the IEEE (263)

Bibliography

Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Hon-Sum Philip Wong. (2001). Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, 89(3), 259â288.

Authors 6

D.J. Frank (first)
R.H. Dennard (additional)
E. Nowak (additional)
P.M. Solomon (additional)
Y. Taur (additional)
Hon-Sum Philip Wong (additional)

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Dates

Type	When
Created	22 years, 11 months ago (Aug. 24, 2002, 2:17 p.m.)
Deposited	4 months, 4 weeks ago (March 23, 2025, 4:23 a.m.)
Indexed	3 hours, 24 minutes ago (Aug. 21, 2025, 1:07 p.m.)
Issued	24 years, 5 months ago (March 1, 2001)
Published	24 years, 5 months ago (March 1, 2001)
Published Print	24 years, 5 months ago (March 1, 2001)

Funders 0

None

BibTeX

@article{Frank_2001, title={Device scaling limits of Si MOSFETs and their application dependencies}, volume={89}, ISSN={0018-9219}, url={http://dx.doi.org/10.1109/5.915374}, DOI={10.1109/5.915374}, number={3}, journal={Proceedings of the IEEE}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Frank, D.J. and Dennard, R.H. and Nowak, E. and Solomon, P.M. and Taur, Y. and Hon-Sum Philip Wong}, year={2001}, month=mar, pages={259–288} }

JSON

{
  "indexed": {
    "date-parts": [
      [
        2025,
        8,
        21
      ]
    ],
    "date-time": "2025-08-21T17:07:36Z",
    "timestamp": 1755796056850,
    "version": "3.40.2"
  },
  "reference-count": 97,
  "publisher": "Institute of Electrical and Electronics Engineers (IEEE)",
  "issue": "3",
  "license": [
    {
      "start": {
        "date-parts": [
          [
            2001,
            3,
            1
          ]
        ],
        "date-time": "2001-03-01T00:00:00Z",
        "timestamp": 983404800000
      },
      "content-version": "vor",
      "delay-in-days": 0,
      "URL": "https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html"
    }
  ],
  "content-domain": {
    "domain": [],
    "crossmark-restriction": false
  },
  "published-print": {
    "date-parts": [
      [
        2001,
        3
      ]
    ]
  },
  "DOI": "10.1109/5.915374",
  "type": "journal-article",
  "created": {
    "date-parts": [
      [
        2002,
        8,
        24
      ]
    ],
    "date-time": "2002-08-24T18:17:23Z",
    "timestamp": 1030213043000
  },
  "page": "259-288",
  "source": "Crossref",
  "is-referenced-by-count": 1230,
  "title": "Device scaling limits of Si MOSFETs and their application dependencies",
  "prefix": "10.1109",
  "volume": "89",
  "author": [
    {
      "given": "D.J.",
      "family": "Frank",
      "sequence": "first",
      "affiliation": []
    },
    {
      "given": "R.H.",
      "family": "Dennard",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "E.",
      "family": "Nowak",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "P.M.",
      "family": "Solomon",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "given": "Y.",
      "family": "Taur",
      "sequence": "additional",
      "affiliation": []
    },
    {
      "family": "Hon-Sum Philip Wong",
      "sequence": "additional",
      "affiliation": []
    }
  ],
  "member": "263",
  "reference": [
    {
      "key": "ref1",
      "article-title": "Method and apparatus for controlling electric cur-rents",
      "volume-title": "U.S. Patent 1 745 175",
      "author": "Lilienfeld",
      "year": "1930"
    },
    {
      "article-title": "Silicon-silicon dioxide field induced surface devices",
      "volume-title": "IRE Solid-State Device Res. Conf.",
      "author": "Kahng",
      "key": "ref2"
    },
    {
      "key": "ref3",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/5.658761"
    },
    {
      "article-title": "Semiconductor Industry Association (SIA)",
      "volume-title": "International Technology Roadmap for Semiconductors, 1999 ed.",
      "year": "1999",
      "key": "ref4"
    },
    {
      "key": "ref5",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/5.371968"
    },
    {
      "key": "ref6",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/5.573737"
    },
    {
      "key": "ref7",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/5.573738"
    },
    {
      "key": "ref8",
      "first-page": "60",
      "article-title": "MOS scaling beyond 0.1\u03bcm",
      "volume-title": "Silicon Nanoelectronics Workshop",
      "author": "Sugii"
    },
    {
      "key": "ref9",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/5.752515"
    },
    {
      "key": "ref10",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/16.141237"
    },
    {
      "key": "ref11",
      "first-page": "553",
      "article-title": "Monte Carlo simulation of a 30 nm dual-gate MOSFET: How far can Si go?",
      "volume-title": "IEDM Tech. Dig.",
      "author": "Frank"
    },
    {
      "key": "ref12",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/iedm.1998.746385"
    },
    {
      "key": "ref13",
      "first-page": "47",
      "article-title": "Fringing fields in sub-0.1 \u00b5m FD SOI MOSFETs: Optimization of the device architecture",
      "volume-title": "Proc. ULIS 2000 Workshop",
      "author": "Ernst"
    },
    {
      "key": "ref14",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/JSSC.1974.1050511"
    },
    {
      "key": "ref15",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/JPROC.1999.752521"
    },
    {
      "key": "ref16",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/iedm.1997.650344"
    },
    {
      "key": "ref17",
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      "DOI": "10.1109/T-ED.1984.21550"
    },
    {
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      "DOI": "10.1007/978-1-4615-5685-5_2"
    },
    {
      "key": "ref19",
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    },
    {
      "key": "ref20",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/IEDM.1981.190042"
    },
    {
      "article-title": "Small-geometry MOS transistors: Physics and modeling of surface-and buried-channel MOSFETs",
      "year": "1984",
      "author": "Nguyen",
      "key": "ref21"
    },
    {
      "key": "ref22",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/JSSC.1972.1050260"
    },
    {
      "key": "ref23",
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      "DOI": "10.1109/IEDM.1999.824182"
    },
    {
      "key": "ref24",
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      "DOI": "10.1109/55.568766"
    },
    {
      "key": "ref25",
      "first-page": "555",
      "article-title": "Modeling and characterization of n+-and p+-polysilicon-gated ultra thin oxides (pp.21-26A)",
      "volume-title": "Proc. Symp. VLSI Technol.",
      "author": "Lo"
    },
    {
      "key": "ref26",
      "doi-asserted-by": "publisher",
      "DOI": "10.1147/rd.391.0245"
    },
    {
      "key": "ref27",
      "first-page": "789",
      "article-title": "25 nm CMOS design consid-erations",
      "volume-title": "IEDM Tech. Dig.",
      "author": "Taur"
    },
    {
      "key": "ref28",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/VLSIT.2000.852814"
    },
    {
      "key": "ref29",
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    },
    {
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    },
    {
      "key": "ref31",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/55.863106"
    },
    {
      "key": "ref32",
      "first-page": "737",
      "article-title": "Straddle-gate transistor: Changing MOSFET channel length between off-and on-state toward achieving tunneling-defined limit of field-effect",
      "volume-title": "IEDM Tech. Dig.",
      "author": "Welser"
    },
    {
      "key": "ref33",
      "first-page": "47",
      "article-title": "Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs",
      "volume-title": "Proc. Silicon Nanoelectronics Workshop",
      "author": "Frank"
    },
    {
      "key": "ref34",
      "doi-asserted-by": "publisher",
      "DOI": "10.1109/16.678551"
    },
    {
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    },
    {
      "key": "ref36",
      "first-page": "26",
      "article-title": "Direct source-drain tunneling current in subthreshold region of sub-10-gate EJ-MOSFETs",
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      "author": "Kawaura"
    },
    {
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    },
    {
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  ],
  "container-title": "Proceedings of the IEEE",
  "original-title": [],
  "link": [
    {
      "URL": "http://xplorestaging.ieee.org/ielx5/5/19772/00915374.pdf?arnumber=915374",
      "content-type": "unspecified",
      "content-version": "vor",
      "intended-application": "similarity-checking"
    }
  ],
  "deposited": {
    "date-parts": [
      [
        2025,
        3,
        23
      ]
    ],
    "date-time": "2025-03-23T08:23:30Z",
    "timestamp": 1742718210000
  },
  "score": 1,
  "resource": {
    "primary": {
      "URL": "http://ieeexplore.ieee.org/document/915374/"
    }
  },
  "subtitle": [],
  "short-title": [],
  "issued": {
    "date-parts": [
      [
        2001,
        3
      ]
    ]
  },
  "references-count": 97,
  "journal-issue": {
    "issue": "3"
  },
  "URL": "http://dx.doi.org/10.1109/5.915374",
  "relation": {},
  "ISSN": [
    "0018-9219"
  ],
  "subject": [],
  "container-title-short": "Proc. IEEE",
  "published": {
    "date-parts": [
      [
        2001,
        3
      ]
    ]
  }
}