DOI: 10.1109/16.887014. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

10.1109/16.887014

Crossref journal-article

Institute of Electrical and Electronics Engineers (IEEE)

IEEE Transactions on Electron Devices (263)

Bibliography

Chenming Hu, Bokor, J., Tsu-Jae King, Anderson, E., Kuo, C., Asano, K., Takeuchi, H., Kedzierski, J., Wen-Chin Lee, & Hisamoto, D. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47(12), 2320â2325.

Authors 10

Chenming Hu (first)
J. Bokor (additional)
Tsu-Jae King (additional)
E. Anderson (additional)
C. Kuo (additional)
K. Asano (additional)
H. Takeuchi (additional)
J. Kedzierski (additional)
Wen-Chin Lee (additional)
D. Hisamoto (additional)

References 13 Referenced 1,297

10.1109/16.81634
{'key': 'ref11', 'first-page': '950', 'article-title': 'a 0.1 <formula><tex>$\\mu$</tex></formula>m-gate elevated source and drain mosfet fabricated by phase-shifted lithography', 'author': 'kimura', 'year': '1991', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / a 0.1 <formula><tex>$\mu$</tex></formula>m-gate elevated source and drain mosfet fabricated by phase-shifted lithography by kimura (1991)
{'key': 'ref12', 'first-page': '117', 'article-title': "reliable tantalum gate fully-depleted-soi mosfet's with 0.15 <formula><tex>$\\mu$</tex></formula>m gate length by low-temperature processing below 500 c", 'author': 'ushiki', 'year': '1996', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / reliable tantalum gate fully-depleted-soi mosfet's with 0.15 <formula><tex>$\mu$</tex></formula>m gate length by low-temperature processing below 500 c by ushiki (1996)
10.1109/16.277374
10.1109/IEDM.1994.383315
10.1109/16.249482
10.1109/IEDM.1993.347211
10.1109/16.669563
{'key': 'ref8', 'first-page': '345', 'article-title': 'novel polysilicon/tin stacked-gate structure for fully-depleted soi/cmos', 'author': 'hwang', 'year': '1992', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / novel polysilicon/tin stacked-gate structure for fully-depleted soi/cmos by hwang (1992)
10.1109/16.285027
10.1109/VLSIT.1993.760231
10.1109/IEDM.1992.307422
10.1109/IEDM.1998.746531

Dates

Type	When
Created	22 years, 11 months ago (Aug. 24, 2002, 2:17 p.m.)
Deposited	3 years, 8 months ago (Nov. 29, 2021, 2:08 p.m.)
Indexed	12 hours, 39 minutes ago (Aug. 21, 2025, 12:35 p.m.)
Issued	25 years, 7 months ago (Jan. 1, 2000)
Published	25 years, 7 months ago (Jan. 1, 2000)
Published Print	25 years, 7 months ago (Jan. 1, 2000)

Funders 0

None

BibTeX

@article{Chenming_Hu_2000, title={FinFET-a self-aligned double-gate MOSFET scalable to 20 nm}, volume={47}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.887014}, DOI={10.1109/16.887014}, number={12}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Chenming Hu and Bokor, J. and Tsu-Jae King and Anderson, E. and Kuo, C. and Asano, K. and Takeuchi, H. and Kedzierski, J. and Wen-Chin Lee and Hisamoto, D.}, year={2000}, pages={2320–2325} }

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