DOI: 10.1109/16.293306. Scaling the MOS transistor below 0.1 μm: methodology, device structures, and technology requirements

Scaling the MOS transistor below 0.1 μm: methodology, device structures, and technology requirements

10.1109/16.293306

Crossref journal-article

Institute of Electrical and Electronics Engineers (IEEE)

IEEE Transactions on Electron Devices (263)

Bibliography

Fiegna, C., Iwai, H., Wada, T., Saito, M., Sangiorgi, E., & Ricco, B. (1994). Scaling the MOS transistor below 0.1 Î¼m: methodology, device structures, and technology requirements. IEEE Transactions on Electron Devices, 41(6), 941â951.

Authors 6

C. Fiegna (first)
H. Iwai (additional)
T. Wada (additional)
M. Saito (additional)
E. Sangiorgi (additional)
B. Ricco (additional)

References 31 Referenced 91

{'key': 'ref31', 'first-page': '375', 'article-title': 'BSA technology for sub-100 nm deep base bipolar transistors', 'author': 'takemura', 'year': '1987', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / BSA technology for sub-100 nm deep base bipolar transistors by takemura (1987)
{'key': 'ref30', 'first-page': '994', 'article-title': 'Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 Si MOSFETs', 'author': 'manchanda', 'year': '1992', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 Si MOSFETs by manchanda (1992)
10.1103/PhysRev.163.816
10.1016/0038-1101(90)90138-5
10.1109/VLSIT.1993.760264
10.1109/16.123489
{'key': 'ref14', 'year': '1990', 'journal-title': 'Silicon-on-Insulator Technology Materials for VLSI'} / Silicon-on-Insulator Technology Materials for VLSI (1990)
10.1109/SOI.1992.664828
{'key': 'ref16', 'first-page': '675', 'article-title': '0.1?m-gate, ultrathinfilm CMOS devices using SIMOX substrate with 80 nm-thick buried oxide layer', 'author': 'omura', 'year': '1992', 'journal-title': 'IEDM Tech Dig'} / IEDM Tech Dig / 0.1?m-gate, ultrathinfilm CMOS devices using SIMOX substrate with 80 nm-thick buried oxide layer by omura (1992)
10.1109/IEDM.1993.347385
10.1109/16.119031
10.1109/IEDM.1992.307423
10.1109/55.17823
{'key': 'ref4', 'first-page': '490', 'article-title': '3 V operation of 70 nm gate length MOSFET with new double punehthrough stopper structure', 'author': 'hashimoto', 'year': '1992', 'journal-title': 'Ext Abstr Int Conf Solid State Devices and Materials'} / Ext Abstr Int Conf Solid State Devices and Materials / 3 V operation of 70 nm gate length MOSFET with new double punehthrough stopper structure by hashimoto (1992)
{'key': 'ref27', 'first-page': '81', 'article-title': 'Universal mobility-field curves for electrons and holes in MOSFET inversion layers', 'author': 'watt', 'year': '1981', 'journal-title': '1981 Symp VLSI Technol Tech Dig'} / 1981 Symp VLSI Technol Tech Dig / Universal mobility-field curves for electrons and holes in MOSFET inversion layers by watt (1981)
10.1063/1.105717
{'key': 'ref6', 'first-page': '487', 'article-title': 'High speed 0.1 pm CMOS devices operating at room temperature', 'author': 'toriumi', 'year': '1992', 'journal-title': 'Ext Abstr Int Conf Solid State Devices and Materials'} / Ext Abstr Int Conf Solid State Devices and Materials / High speed 0.1 pm CMOS devices operating at room temperature by toriumi (1992)
10.1109/IEDM.1992.307454
10.1109/IEDM.1992.307422
{'key': 'ref8', 'first-page': '23', 'article-title': 'Limits on gate insulator thickness for MISFET operation in pure-oxide and nitride-oxide gate cases', 'author': 'morimoto', 'year': '1991', 'journal-title': 'Ext Abstr Int Conf Solid State Devices and Materials'} / Ext Abstr Int Conf Solid State Devices and Materials / Limits on gate insulator thickness for MISFET operation in pure-oxide and nitride-oxide gate cases by morimoto (1991)
10.1109/IEDM.1992.307501
10.1109/IEDM.1991.235433
{'key': 'ref9', 'author': 'brews', 'year': '1990', 'journal-title': 'High Speed Semiconductor Devices'} / High Speed Semiconductor Devices by brews (1990)
10.1109/IEDM.1990.237087
10.1016/0010-4655(91)90225-A
10.1103/PhysRevB.33.7263
10.1016/0038-1101(80)90033-7
10.1016/0038-1101(89)90291-8
{'key': 'ref23', 'first-page': '108', 'article-title': 'Development and application of a highspeed 2-dimensional; time dependent device simulator (MOS2C)', 'author': 'wada', 'year': '1985', 'journal-title': 'Proc Nasecode IV'} / Proc Nasecode IV / Development and application of a highspeed 2-dimensional; time dependent device simulator (MOS2C) by wada (1985)
10.1109/IEDM.1991.235346
10.1109/16.199369

Dates

Type	When
Created	22 years, 11 months ago (Aug. 24, 2002, 4:40 p.m.)
Deposited	3 years, 8 months ago (Nov. 29, 2021, 2:09 p.m.)
Indexed	1 year, 1 month ago (July 5, 2024, 8:13 p.m.)
Issued	31 years, 2 months ago (June 1, 1994)
Published	31 years, 2 months ago (June 1, 1994)
Published Print	31 years, 2 months ago (June 1, 1994)

Funders 0

None

BibTeX

@article{Fiegna_1994, title={Scaling the MOS transistor below 0.1 μm: methodology, device structures, and technology requirements}, volume={41}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.293306}, DOI={10.1109/16.293306}, number={6}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Fiegna, C. and Iwai, H. and Wada, T. and Saito, M. and Sangiorgi, E. and Ricco, B.}, year={1994}, month=jun, pages={941–951} }

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