Abstract
We developed a multilevel lithography process to fabricate graphene p-n-p junctions with contactless, suspended top gates. This fabrication procedure minimizes damage or doping to the single atomic layer, which is only exposed to conventional resists and developers. The process does not require special equipment for depositing gate dielectrics or releasing sacrificial layers, and is compatible with annealing procedures that improve device mobility. Using this technique, we fabricate graphene devices with suspended local top gates, where the creation of high quality graphene p-n-p junctions is confirmed by transport data at zero and high magnetic fields.
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Dates
Type | When |
---|---|
Created | 17 years, 3 months ago (May 21, 2008, 12:11 p.m.) |
Deposited | 3 months ago (May 29, 2025, 2:05 p.m.) |
Indexed | 1 month ago (July 30, 2025, 6:50 a.m.) |
Issued | 17 years, 3 months ago (May 19, 2008) |
Published | 17 years, 3 months ago (May 19, 2008) |
Published Online | 17 years, 3 months ago (May 20, 2008) |
Published Print | 17 years, 3 months ago (May 19, 2008) |
@article{Liu_2008, title={Fabrication of graphene p-n-p junctions with contactless top gates}, volume={92}, ISSN={1077-3118}, url={http://dx.doi.org/10.1063/1.2928234}, DOI={10.1063/1.2928234}, number={20}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={Liu, Gang and Velasco, Jairo and Bao, Wenzhong and Lau, Chun Ning}, year={2008}, month=may }