Abstract
Semiconductor-based single-electron transistors have been fabricated using heterostructure nanowire growth, by introducing a double barrier of InP into InAs nanowires. From electrical measurements, we observe a charging energy of 4 meV for the approximately 55 nm diameter and 100 nm long InAs islands between the InP barriers. The Coulomb blockade can be periodically lifted as a function of gate voltage for all devices, which is a typical signature of single-island transistors. Homogeneous InAs nanowires show no such effect for the corresponding voltage ranges.
References
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Dates
Type | When |
---|---|
Created | 21 years, 11 months ago (Sept. 8, 2003, 11:02 a.m.) |
Deposited | 1 year, 6 months ago (Feb. 3, 2024, 8:21 p.m.) |
Indexed | 2 months, 2 weeks ago (June 14, 2025, 11:28 a.m.) |
Issued | 21 years, 11 months ago (Sept. 8, 2003) |
Published | 21 years, 11 months ago (Sept. 8, 2003) |
Published Print | 21 years, 11 months ago (Sept. 8, 2003) |
@article{Thelander_2003, title={Single-electron transistors in heterostructure nanowires}, volume={83}, ISSN={1077-3118}, url={http://dx.doi.org/10.1063/1.1606889}, DOI={10.1063/1.1606889}, number={10}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={Thelander, C. and Mårtensson, T. and Björk, M. T. and Ohlsson, B. J. and Larsson, M. W. and Wallenberg, L. R. and Samuelson, L.}, year={2003}, month=sep, pages={2052–2054} }