Abstract
We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.
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Dates
Type | When |
---|---|
Created | 23 years, 1 month ago (July 26, 2002, 8:44 a.m.) |
Deposited | 1 year, 6 months ago (Feb. 3, 2024, 3:27 p.m.) |
Indexed | 3 months, 3 weeks ago (May 3, 2025, 1:10 a.m.) |
Issued | 24 years, 1 month ago (July 16, 2001) |
Published | 24 years, 1 month ago (July 16, 2001) |
Published Print | 24 years, 1 month ago (July 16, 2001) |
@article{Black_2001, title={Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication}, volume={79}, ISSN={1077-3118}, url={http://dx.doi.org/10.1063/1.1383805}, DOI={10.1063/1.1383805}, number={3}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={Black, C. T. and Guarini, K. W. and Milkove, K. R. and Baker, S. M. and Russell, T. P. and Tuominen, M. T.}, year={2001}, month=jul, pages={409–411} }