Abstract
The concept of carrier pocket engineering is applied to strained Si/Ge superlattices to obtain a large thermoelectric figure of merit ZT. In this system, the effect of the lattice strain at the Si/Ge interfaces provides another degree of freedom to control the conduction band structure of the superlattice. We explore various geometries and structures to optimize ZT for the whole three-dimensional superlattice. The resultant ZT, calculated for a symmetrized Si(20 Å)/Ge(20 Å) superlattice grown on a (111) oriented Si0.5Ge0.5 substrate, is 0.96 at 300 K and is shown to increase significantly at elevated temperatures. Such a superlattice can be grown using molecular beam epitaxy.
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Dates
Type | When |
---|---|
Created | 23 years ago (July 26, 2002, 9:29 a.m.) |
Deposited | 1 year, 6 months ago (Feb. 3, 2024, 12:04 p.m.) |
Indexed | 3 months, 1 week ago (May 13, 2025, 8:08 p.m.) |
Issued | 25 years, 10 months ago (Oct. 18, 1999) |
Published | 25 years, 10 months ago (Oct. 18, 1999) |
Published Print | 25 years, 10 months ago (Oct. 18, 1999) |
@article{Koga_1999, title={Carrier pocket engineering applied to “strained” Si/Ge superlattices to design useful thermoelectric materials}, volume={75}, ISSN={1077-3118}, url={http://dx.doi.org/10.1063/1.125040}, DOI={10.1063/1.125040}, number={16}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={Koga, T. and Sun, X. and Cronin, S. B. and Dresselhaus, M. S.}, year={1999}, month=oct, pages={2438–2440} }