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journal-article
Springer Science and Business Media LLC
Nature (297)
References
29
Referenced
664
-
Ferain, I., Colinge, A. A. & Colinge, J.-P. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011)
(
10.1038/nature10676
) / Nature by I Ferain (2011) -
del Alamo, J. A. Nanometre-scale electronics with III–V compound semiconductors. Nature 479, 317–323 (2011)
(
10.1038/nature10677
) / Nature by JA del Alamo (2011) -
Seabaugh, A. C. & Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010)
(
10.1109/JPROC.2010.2070470
) / Proc. IEEE by AC Seabaugh (2010) -
Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011)
(
10.1038/nature10679
) / Nature by AM Ionescu (2011) -
Radosavljevic, M. et al. Advanced high-k gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications. IEDM Tech. Dig. 319–322 (2009)
(
10.1109/IEDM.2009.5424361
) -
Kim, S. H. et al. Electron mobility enhancement of extremely thin body In0. 7Ga0. 3As-on-insulator metal-oxide-semiconductor field-effect transistors on Si substrates by metal-oxide-semiconductor interface buffer layer. Appl. Phys. Exp. 5, 014201 (2012)
(
10.1143/APEX.5.014201
) / Appl. Phys. Exp. by SH Kim (2012) -
Wu, Y. Q. et al. 0.8-V supply voltage deep-submicrometer inversion-mode In0. 75Ga0. 25As MOSFET. IEEE Elec. Dev. Lett. 30, 700–702 (2009)
(
10.1109/LED.2009.2022346
) / IEEE Elec. Dev. Lett. by YQ Wu (2009) -
Radosavljevic, M. et al. Non-planar, multi-gate InGaAs quantum well field effect transistors with high-k gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications. IEDM Tech Dig. 126–129. (2010)
(
10.1109/IEDM.2010.5703306
) -
Radosavljevic, M. et al. Electrostatic improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-k gate dielectric and scaled gate-to-drain/gate-to-source separation. IEDM Tech. Dig. 765–768. (2011)
(
10.1109/IEDM.2011.6131661
) -
Wieder, H. H. Surface and interface barriers of In x Ga1−x As binary and ternary alloys. J. Vac. Sci. Technol. B 21, 1915–1919 (2003)
(
10.1116/1.1588646
) / J. Vac. Sci. Technol. B by HH Wieder (2003) -
Takato, H. et al. Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s. IEEE Trans. Electron. Dev. 38, 573–578 (1991)
(
10.1109/16.75168
) / IEEE Trans. Electron. Dev. by H Takato (1991) -
Gu, J. J. et al. First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach. IEDM Tech. Dig. 769–772. (2011)
(
10.1109/IEDM.2011.6131662
) -
Tomioka, K., Yoshimura, M. & Fukui, T. Vertical In0. 7Ga0. 3As nanowire surrounding-gate transistors with high-k gate dielectrics on Si substrate. IEDM Tech. Dig. 773–776. (2011)
(
10.1109/IEDM.2011.6131663
) -
Xuan, Y. et al. Submicrometer inversion-type enhancement-mode InGaAs MOSFET with atomic-layer-deposited Al2O3 as gate dielectric. IEEE Elec. Dev. Lett 28, 935–938 (2007)
(
10.1109/LED.2007.906436
) / IEEE Elec. Dev. Lett by Y Xuan (2007) -
Ishii, H. et al. High electron mobility metal-insulator-semiconductor field-effect transistors fabricated on (111)-oriented InGaAs channels. Appl. Phys. Exp. 2, 121101 (2009)
(
10.1143/APEX.2.121101
) / Appl. Phys. Exp. by H Ishii (2009) - Kim, D.-H. et al. 50-nm E-mode In0. 7Ga0. 3As PHEMTs on 100-nm InP substrate with f max > 1 THz. IEDM Tech. Dig. 692–695. (2010)
-
Furukawa, Y. et al. Control of N content of GaPN grown by molecular beam epitaxy and growth of GaPN lattice matched on Si(100) substrate. Jpn. J. Appl. Phys. 41, 528–532 (2002)
(
10.1143/JJAP.41.528
) / Jpn. J. Appl. Phys. by Y Furukawa (2002) -
Tomioka, K., Motohisa, J., Hara, S. & Fukui, T. Control of InAs nanowire growth directions on Si. Nano Lett. 8, 3475–3480 (2008)
(
10.1021/nl802398j
) / Nano Lett. by K Tomioka (2008) -
Tomioka, K. et al. Selective-area growth of vertically aligned GaAs and GaAs/AlGaAs core-shell nanowires on Si(111) substrate. Nanotechnology 20, 145302 (2009)
(
10.1088/0957-4484/20/14/145302
) / Nanotechnology by K Tomioka (2009) -
Noborisaka, J. et al. Electrical characterization of InGaAs nanowire-top-gate field-effect transistors by selective-area metal organic vapor phase epitaxy. Jpn. J. Appl. Phys. 46, 7562–7568 (2007)
(
10.1143/JJAP.46.7562
) / Jpn. J. Appl. Phys. by J Noborisaka (2007) -
Rehnstedt, C. et al. Vertical InAs nanowire wrap gate transistors on Si substrate. IEEE Trans. Electron. Dev. 55, 3037–3041 (2008)
(
10.1109/TED.2008.2005179
) / IEEE Trans. Electron. Dev. by C Rehnstedt (2008) -
Tanaka, T. et al. Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates. Appl. Phys. Exp. 3, 025003 (2010)
(
10.1143/APEX.3.025003
) / Appl. Phys. Exp. by T Tanaka (2010) -
Wernersson, L.-E., Thelander, C., Lind, E. & Samuelson, L. III–V nanowires—extending a narrowing road. Proc. IEEE 98, 2047–2060 (2010)
(
10.1109/JPROC.2010.2065211
) / Proc. IEEE by L-E Wernersson (2010) -
Ghalamestani, S. G. et al. Uniform and position controlled InAs nanowires on 2′′ Si substrate for transistor applications. Nanotechnology 23, 015302 (2012)
(
10.1088/0957-4484/23/1/015302
) / Nanotechnology by SG Ghalamestani (2012) -
Mimura, T., Hiyamizu, S., Fujii, T. & Nanbu, K. A new field-effect transistor with selectively doped GaAs/n-Al x Ga1−x As heterojunctions. Jpn. J. Appl. Phys. 19, L225–L227 (1980)
(
10.1143/JJAP.19.L225
) / Jpn. J. Appl. Phys. by T Mimura (1980) -
Tan, I.-H., Snider, G. L., Chang, L. D. & Hu, E. L. A self-consistent solution of Schrodinger-Poisson equations using nonuniform mesh. J. Appl. Phys. 68, 4071–4076 (1990)
(
10.1063/1.346245
) / J. Appl. Phys. by I-H Tan (1990) -
Takagi, S., Toriumi, A., Iwase, M. & Tango, H. On the universality of inversion layer mobility in Si MOSFET’s: part I—effects of substrate impurity concentration. IEEE Trans. Electron. Dev. 41, 2357–2362 (1994)
(
10.1109/16.337449
) / IEEE Trans. Electron. Dev. by S Takagi (1994) - ITRS. International Technology Roadmap for Semiconductors http://www.itrs.net/Links/2011ITRS/Home2011.htm (ITRS, 2011)
-
Galindo, P. L. et al. The peak pairs algorithm for strain mapping from HRTEM images. Ultramicroscopy 107, 1186–1193 (2007)
(
10.1016/j.ultramic.2007.01.019
) / Ultramicroscopy by PL Galindo (2007)
Dates
Type | When |
---|---|
Created | 13 years ago (Aug. 1, 2012, 5:08 a.m.) |
Deposited | 2 years, 3 months ago (May 18, 2023, 2:02 p.m.) |
Indexed | 4 days, 4 hours ago (Aug. 23, 2025, 1:08 a.m.) |
Issued | 13 years ago (Aug. 1, 2012) |
Published | 13 years ago (Aug. 1, 2012) |
Published Online | 13 years ago (Aug. 1, 2012) |
Published Print | 13 years ago (Aug. 1, 2012) |
@article{Tomioka_2012, title={A III–V nanowire channel on silicon for high-performance vertical transistors}, volume={488}, ISSN={1476-4687}, url={http://dx.doi.org/10.1038/nature11293}, DOI={10.1038/nature11293}, number={7410}, journal={Nature}, publisher={Springer Science and Business Media LLC}, author={Tomioka, Katsuhiro and Yoshimura, Masatoshi and Fukui, Takashi}, year={2012}, month=aug, pages={189–192} }