DOI: 10.1007/bf01250732. Scaling of MOS technology to submicrometer feature sizes

Scaling of MOS technology to submicrometer feature sizes

10.1007/bf01250732

Crossref journal-article

Springer Science and Business Media LLC

Analog Integrated Circuits and Signal Processing (297)

Bibliography

Mead, C. A. (1994). Scaling of MOS technology to submicrometer feature sizes. Analog Integrated Circuits and Signal Processing, 6(1), 9â25.

Authors 1

Carver A. Mead (first)

References 34 Referenced 46

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C. Mead,Analog VLSI and Neural Systems, Addison-Wesley: Reading, MA, 1989. / Analog VLSI and Neural Systems by C. Mead (1989)
B. Hoeneisen and C.A. Mead, ?Fundamental limitations in microelectronics. I: MOS technology,?Solid-State Electron., Vol. 15, pp. 819?829, 1972. (10.1016/0038-1101(72)90103-7) / Solid-State Electron. by B. Hoeneisen (1972)
M. Nagata, ?Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond,?IEEE J. Solid-State Circuits, Vol. 27, pp. 465?472, 1992. (10.1109/4.126533) / IEEE J. Solid-State Circuits by M. Nagata (1992)
B. Davari, W.-H. Chang, K.E. Petrillo, C.Y. Wong, D. Moy, Y. Taur, M.R. Wordeman, J.Y-C. Sun, C.C-H. Hsu, and M.R. Polcari, ?A high-performance 0.25-�m CMOS technology. II: Technology,?IEEE Trans. Electron Dev., Vol. 39, pp. 967?975, 1992. (10.1109/16.127490) / IEEE Trans. Electron Dev. by B. Davari (1992)
W.-H. Chang, B. Davari, M. Wordeman, Y. Taur, C.C-H. Hsu, and M.D. Rodriguez, ?A high-performance 0.25-�m CMOS technology. I: Design and characterization,?IEEE Trans. Electron Dev., Vol. 39, pp. 959?966, 1992. (10.1109/16.127489) / IEEE Trans. Electron Dev. by W.-H. Chang (1992)
A. Bryant, B. El-Kareh, T. Furukawa, W.P. Noble, E.J. Nowak, W. Schwittek, and W. Tonti, ?A fundamental performance limit of optimized 3.3-V sub-quarter-micrometer fully overlapped LDD MOSFETs,?IEEE Trans. Electron Dev.., Vol. 39, pp. 1208?1215, 1992. (10.1109/16.129105) / IEEE Trans. Electron Dev.. by A. Bryant (1992)
R.H. Yan, K.F. Lee, D.Y. Jeon, Y.O. Kim, D.M. Tennant, E.H. Westerwick, G.M. Chin, M.D. Morris, K. Early, and P. Mulgren, ?High-performance deep-submicrometer Si MOSFETs using vertical doping engineering,?IEEE Trans. Electron Dev., Vol. 39, p. 2639, 1992. (10.1109/16.163487) / IEEE Trans. Electron Dev. by R.H. Yan (1992)
Y. Yamaguchi, A. Ishibashi, M. Shimizu, T. Nishimura, K. Tsukamoto, K. Horie, and Y. Akasaka, ?A high-speed 0.6-�m 16K CMOS gate array on a thin SIMOX film,?IEEE Trans. Electron Dev., Vol. 1, pp. 179?185, 1993. (10.1109/16.249442) / IEEE Trans. Electron Dev. by Y. Yamaguchi (1993)
M. Iwase, T. Mizuno, M. Takahashi, H. Niiyama, M. Fukumoto, K. Ishida, S. Inaba, Y. Takigami, A. Sanda, A. Toriumi, and M. Yoshimi, ?High-performance 0.10-�m CMOS devices operating at room temperature,?IEEE Electron Dev. Lett., Vol. 14, pp. 51?53, 1993. (10.1109/55.215105) / IEEE Electron Dev. Lett. by M. Iwase (1993)
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Dates

Type	When
Created	20 years, 6 months ago (Feb. 26, 2005, 3:16 p.m.)
Deposited	8 months ago (Dec. 24, 2024, 12:24 p.m.)
Indexed	3 months, 1 week ago (May 18, 2025, 1:22 a.m.)
Issued	31 years, 1 month ago (July 1, 1994)
Published	31 years, 1 month ago (July 1, 1994)
Published Print	31 years, 1 month ago (July 1, 1994)

Funders 0

None

BibTeX

@article{Mead_1994, title={Scaling of MOS technology to submicrometer feature sizes}, volume={6}, ISSN={1573-1979}, url={http://dx.doi.org/10.1007/bf01250732}, DOI={10.1007/bf01250732}, number={1}, journal={Analog Integrated Circuits and Signal Processing}, publisher={Springer Science and Business Media LLC}, author={Mead, Carver A.}, year={1994}, month=jul, pages={9–25} }

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