DOI: 10.1007/3-540-16766-8_16. Exploiting hierarchy in VLSI design

Exploiting hierarchy in VLSI design

10.1007/3-540-16766-8_16

Crossref book-chapter

Springer Berlin Heidelberg

Lecture Notes in Computer Science (297)

Bibliography

Lengauer, T. (1986). Exploiting hierarchy in VLSI design. VLSI Algorithms and Architectures, 180â193.

Authors 1

T. Lengauer (first)

References 43 Referenced 11

Arnold, M.H./Ousterhout, J.K.: Lyra: A new approach to geometric design rule checking. Proc. 19th Design Automation Conference (1982), 530–536 (10.1109/DAC.1982.1585549)
Brayton, R.K./Brenner, N.L./Chen, C.L./DeMicheli, G./McMullen, C.T./Otten, R.H.J.M.: The YORKTOWN Silicon Compiler. Proc. of International Symposium on Circuits and Systems (ISCAS '85) (1985)
Breuer, M.A./Kumar, A.: A methodology for custom VLSI layout. IEEE trans. Circuits and Systems. CAS-30,6 (1983), 358–364 (10.1109/TCS.1983.1085362) / IEEE trans. Circuits and Systems by M.A. Breuer (1983)
Bentley, J.L./Ottmann, T./Widmayer, P.: The complexity of manipulating hierarchically defined sets of rectangles. In: Advances in Computing Research (JAI Press Inc.) 1 (1983), 127–158 / Advances in Computing Research by J.L. Bentley (1983)
Bryant, R.E.: A switch-level model and simulator for MOS digital systems. IEEE Trans. Comput. C-33,2 (1984), 160–177 (10.1109/TC.1984.1676408) / IEEE Trans. Comput. by R.E. Bryant (1984)
Rammig, F.J.: Mixed-level modelling and simulation of VLSI systems. Advances in CAD for VLSI, Vol. II (E. Hörbst, ed.), North-Holland (1986)
Chao, S./Huang, Y./Yan, L.M.: A hierarchical approach for layout versus circuit consistency check. Proc. 17th Design Automation Conference (1980), 269–276 (10.1145/800139.804539)
Chen, M.C./Mead, C.A.: A hierarchical simulator based on formal semantics. Proc. 3rd Caltech VLSI Conference (R.E. Bryant, ed.) (1983), 207–224 (10.1007/978-3-642-95432-0_12)
Entenmann, G./Daniel, S.W.: A fully automatic hierarchical compactor. Proc. 22nd Design Automation Conference (1985), 69–75 (10.1109/DAC.1985.1585914)
Gabow, H.N./Galil, Z./Spencer, T./Tarjan, R.E.: Efficient algorithms for finding minimum spanning trees in undirected and directed graphs. Typescript (1985). To appear in COMBINATORIKA (10.1007/BF02579168)
Gupta, A./Hon, R.W.: HEXT: A hierarchical circuit extractor. Journal of VLSI and Computer Systems 1, 1 (1983), 23–39 / Journal of VLSI and Computer Systems by A. Gupta (1983)
Lengauer, T./Mehlhorn, K.: The HILL system: A design environment for the hierarchical specifcation, compaction, and simulation of integrated circuit layouts. Proc. MIT-Conference on Advanced Research in VLSI (P. Penfield Jr. ed.), Artech House Company (1984), 139–148
Flake, P.L./Moorby, P.R./Musgrave, G.: HILO Mark 2, Hardware description language. Proc. of 5th Conference on Computer Hardware Description Languages and Their Applications (M. Breuer, K. Hartenstein, eds.), North Holland (1981), 95–108
Hon, R.W.: The hierarchical analysis of VLSI designs. Ph.D. Thesis, Computer Science Dep., Carnegie-Mellon University, Pittsburgh, PA (1983) / The hierarchical analysis of VLSI designs by R.W. Hon (1983)
Huang, M.A./Steiglitz, K.: A hierarchical compaction algorithm with low page fault complexity. Proc. of the MIT-Conference on Advanced Research in VLSI (P. Penfield Jr., ed.) (1984), 203–212
Johnson, S.C.: Hierarchical design validation based on rectangles. Proc. MIT Conference on Advanced Research in VLSI (P. Penfield Jr., ed.) (1982), 97–100
Katz, R.H./Chang, E./Bhateja, R.: Version modeling concepts for computer-aided design databases. Report No. UCB/CSD86/270, University of California, Berkeley, CA (1985) / Version modeling concepts for computer-aided design databases by R.H. Katz (1985)
Kingsley, C.: A hierarchical error-tolerant compactor. Proc. 21st Design Automation Conference (1984), 126–132 (10.1109/DAC.1984.1585785)
Keller, K.H./Newton, A.R./Ellis, S.: A symbolic design system for integrated circuits. Proc. 19th Design Automation Conference (1982), 460–466 (10.1109/DAC.1982.1585539)
Lengauer, T.: The complexity of compacting hierarchically specified layouts of integrated circuits. Proc. of 23rd IEEE-FOCS (1982), 358–368 (10.1109/SFCS.1982.92)
Lengauer, T.: Hierarchical graph algorithms. TR-SFB 124, No. 15, FB 10, Universität des Saarlandes, Saarbrücken, West-Germany (1984) / Hierarchical graph algorithms by T. Lengauer (1984)
Lengauer, T.: Efficient solution of biconnectivity problems on hierarchically defined graphs. Proc. of the WG '85 (H. Noltemeier, ed.), Trauner Verlag (1985), 201–216
Lengauer, T.: Efficient algorithms for finding minimum spanning forests of hierarchically defined graphs. Proc. of STACS 86, Springer Lecture Notes in Computer Science No. 216 (1986), 153–170 (10.1007/3-540-16078-7_73)
Lengauer, T.: Hierarchical planarity testing algorithms. Proc. of ICALP 86, Springer Lecture Notes in Computer Science (1986) (10.1007/3-540-16761-7_71)
Mead, C./Conway, L.: Introduction of VLSI systems. Addison-Wesley (1980)
Newell, M.E./Fitzpatrick, D.T.: Exploitation of hierarchy in analyses of integrated circuit artwork. IEEE Trans. on CAD-ICAS, Vol. CAD-1,4 (1982), 192–200 (10.1109/TCAD.1982.1270011) / IEEE Trans. on CAD-ICAS by M.E. Newell (1982)
Rowson, J.A.: Understanding hierarchical design. Ph.D. Thesis, Computer Science Dep., California Institute of Technology, Pasadena, CA (1980) / Understanding hierarchical design by J.A. Rowson (1980)
Savitch, W.J.: Relationship between non-deterministic and deterministic tape complexities. JCSS 4,2 (1970), 177–192 / JCSS by W.J. Savitch (1970)
Scheffer, L.K.: The use of strict hierarchy for verification of integrated circuits. Ph.D. Thesis, Stanford University, Stanford, CA (1984) / The use of strict hierarchy for verification of integrated circuits by L.K. Scheffer (1984)
Shand, M.A.: Hierarchical VLSI artwork analysis. Proc. of VLSI 85 (1985), 415–424 / Proc. of VLSI by M.A. Shand (1985)
Scheffer, L.K./Soetarman, R.: Hierarchical analysis of IC artwork with user-defined rules. IEEE Design & Test (Feb. 1986), 66–74 (10.1109/MDT.1986.294941)
Jerraya, A./Rosier, E./Rougeaux, F.R./Courtois, B.: A hierarchical symbolic design layout tool: STYX. Proc. of VLSI 85 (1985), 329–337 / Proc. of VLSI by A. Jerraya (1985)
Tarolli, G.M./Herman, W.J.: Hierarchical circuit extraction with detailed parasitic capacitance. Proc. 20th Design Automation Conference (1983), 337–345 (10.1109/DAC.1983.1585671)
Tygar, J.D./Ellikson, R.: Efficient netlist comparison using hierarchy and randomization. Proc. 22nd Design Automation Conference (1985), 702–708 (10.1109/DAC.1985.1586019)
Taylor, G.S./Ousterhout, J.K.: Magic's incremental design rule checker. Proc. 21st Design Automation Conference (1984), 160–165 (10.1109/DAC.1984.1585790)
Ullmann, J.D.: Computational aspects of VLSI. Computer Science Press (1984)
Rosenberg, J.: A vertically integrated VLSI design environment. Proc. 20th Design Automation Conference (1983), 31–35 (10.1109/DAC.1983.1585622)
van Vlierberghe, S./Rijmenants, J./Heyns, W.: Symbolic hierarchical artwork generation system. Proc. 22nd Design Automation Conference (1985), 789–793 (10.1109/DAC.1985.1586038)
Wagner, T.J.: Hierarchical layout verification. Proc. 21st Design Automation Conference (1984), 484–489 (10.1109/DAC.1984.1585842)
Whitney, T.: A hierarchical design rule checking algorithm. Lambda (first quarter 1981)
Whitney, T.E.: Hierarchical composition of VLSI circuits. Ph.D. Thesis, Computer Science Dep., California Institute of Technology, Pasadena, CA (1985) / Hierarchical composition of VLSI circuits by T.E. Whitney (1985)
Wong, Y.: Hierarchical circuit verification. Proc. 22nd Design Aut. Conference (1985), 695–701 (10.1145/317825.317965)
Zimmermann, G.: Top-down design of digital systems. Advances in CAD for VLSI, Vol. II (E. Hörbst, ed.), North Holland (1986)

Dates

Type	When
Created	13 years, 6 months ago (Feb. 25, 2012, 1:53 p.m.)
Deposited	4 years, 9 months ago (Nov. 17, 2020, 3:11 p.m.)
Indexed	11 months, 3 weeks ago (Sept. 6, 2024, 6:51 p.m.)
Issued	39 years, 7 months ago (Jan. 1, 1986)
Published	39 years, 7 months ago (Jan. 1, 1986)
Published Online	20 years, 2 months ago (June 1, 2005)
Published Print	39 years, 7 months ago (Jan. 1, 1986)

Funders 0

None

BibTeX

@inbook{Lengauer_1986, title={Exploiting hierarchy in VLSI design}, ISBN={9783540387466}, ISSN={1611-3349}, url={http://dx.doi.org/10.1007/3-540-16766-8_16}, DOI={10.1007/3-540-16766-8_16}, booktitle={VLSI Algorithms and Architectures}, publisher={Springer Berlin Heidelberg}, author={Lengauer, T.}, year={1986}, pages={180–193} }

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    }
  },
  "subtitle": [],
  "short-title": [],
  "issued": {
    "date-parts": [
      [
        1986
      ]
    ]
  },
  "ISBN": [
    "9783540167662",
    "9783540387466"
  ],
  "references-count": 43,
  "URL": "http://dx.doi.org/10.1007/3-540-16766-8_16",
  "relation": {},
  "ISSN": [
    "0302-9743",
    "1611-3349"
  ],
  "subject": [],
  "published": {
    "date-parts": [
      [
        1986
      ]
    ]
  }
}